Verilog结构化设计，模拟出下脚位信号

module top;

wire a,b,c,d;
wire out;

 system_clock #800 clock1(a);
 system_clock #400 clock2(b);
 system_clock #200 clock3(c);
 system_clock #100 clock4(d);

not n0(nota,a);
not n1(notb,b);
not n2(notc,c);
not n3(notd,d);
and a0(f0,nota,notc,d);
and a1(f1,nota,c,notd);
and a2(f2,notb,notc,d);
and a3(f3,notb,c,notd);
or  o0(out,f0,f1,f2,f3);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>2000)$stop;
endmodule

1位Register

因为从低电平开始,所以第一个周期的前半周期的qout是未知的.
module top;
wire data,clock;
reg qout;

system_clock #200 clock1(data);
system_clock #100 clock2(clock);

always@(posedge clock)
begin
   qout=data;
end
endmodule
   
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule