HIERARCHY 的行为模式2位元多工器

本次学到:矩阵与接线的位元定义[]前后放的不一样

module top;
  integer is;
  integer ia[1:0],ib[1:0];
  reg [1:0]a,b;
  reg s;
  wire [1:0]out;

  mux_behavioral mux2(out,a,b,s);

  initial
    begin
      for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)
        begin
          a[0]= ia[0];
          for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+ 1)
            begin
              a[1] = ia[1];
               for (ib[0]=0; ib[0]<=1; ib[0] = ib[0]+1)
                 begin
                   b[0] = ib[0];
                    for (ib[1]=0; ib[1]<=1; ib[1] = ib[1]+ 1)
                     begin
                      b[1] = ib[1];
                        for (is=0; is<=1; is = is + 1)
                       begin
                        s = is;
                 #1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d s=%d out[0]%d out[1]%d",a[0],a[1],b[0],b[1],s,out[0],out[1]);
                      end
                    end
                  end
              end
         end
    end
endmodule

module mux_behavioral(OUT,A,B,SEL);
 output [1:0]OUT;
 input [1:0] A,B;
 input SEL;

mux1 X1(OUT[0],A[0],B[0],SEL);
mux1 X2(OUT[1],A[1],B[1],SEL);

endmodule

module mux1(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;

 not n1(NOT_SEL, SEL);
 and a1 (X, A, NOT_SEL);
 and a2 (Y, SEL, B);
 or  o1 (OUT, X, Y);

endmodule

行为模式 2位元多工器件

s=1 out0=a0
       out1=a1
s=0 out0=b0
       out1=b1



module top;
  integer ia0,ia1,ib0,ib1,is;
  reg  a0,a1,b0,b1,s;
  wire out1,out2;

  mux_behavioral mux1(out1,out2,a0,a1,b0,b1,s);

  initial
    begin
      for (ia0=0; ia0<=1; ia0 = ia0+1)
        begin
          a0 = ia0;
          for (ia1=0; ia1<=1; ia1 = ia1+ 1)
            begin
              a1 = ia1;
               for (ib0=0; ib0<=1; ib0 = ib0+1)
                 begin
                   b0 = ib0;
                   for (ib1=0; ib1<=1; ib1 = ib1+ 1)
                    begin
                     b1 = ib1;
                      for (is=0; is<=1; is = is + 1)
                       begin
                        s = is;
                 #1 $display("a0=%d a1=%d b0=%d b1=%d s=%d out1=%d out2=%d",a0,a1,b0,b1,s,out1,out2);
                       end
                    end
                  end
              end
         end
   end
endmodule

module mux_behavioral(OUT1,OUT2,A0,A1,B0,B1,SEL);
 output OUT1,OUT2;
 input A0,A1,B0,B1,SEL;
 wire  A0,A1,B0,B1,SEL;
 reg   OUT1,OUT2;

always @(A0 or A1 or B0 or B1 or SEL)
 begin
   OUT1 = (A0 & SEL)|(B0 & ~SEL );
   OUT2 = (A1 & SEL)|(B1 & ~SEL );
 end
endmodule

2位多工器

这次课程，更深刻理解模拟的意义。

器件的延迟效应与周期的设置应该相互匹配，不然会出现很多复杂的不需要的脉冲。

module top;

wire A0, A1, B0, B1, SEL , NOT_SEL , X , Y , Z, W, OUT0, OUT1;

system_clock #1600clock1(A0);
system_clock #800clock2(A1);
system_clock #400clock3(B0);
system_clock #200 clock4(B1);
system_clock #100 clock5(SEL);

not n1(NOT_SEL, SEL);

and a1(X, A0, SEL);
and a2(Y, A1, SEL);
and a3(Z, B0, NOT_SEL);
and a4(W, B1, NOT_SEL);

or o1(OUT0, X , Z);
or o2(OUT1, Y , W);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>2000)$stop;

endmodule


test_four_practice1位多工器

module top;
wire A, B, SEL , NOT_SEL , X , Y , OUT;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(SEL);
not n1(NOT_SEL, SEL);
and a1(X, A, NOT_SEL);
and a2(Y,SEL, B);
or o1(OUT, X , Y);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule

test_three_practice

这是关于二选一选择器的设计的模拟。
本次学习的疑问在于
1.module top与module mux的差别。
2.OUT中瞬间产生的尖刺电压。



module top; 

wire A, B, SEL , NOT_SEL , X , Y , OUT;

system_clock #400 clock1(A); 
system_clock #200 clock2(B);
system_clock #100 clock3(SEL);

not n1(NOT_SEL, SEL);

and a1(X, A, SEL);
and a2(Y, NOT_SEL, B);

or o1(OUT, X , Y);

endmodule 

module system_clock(clk); 
parameter PERIOD=100; 
output clk; 
reg clk; 

initial clk=0; 

always 
 begin 
#(PERIOD/2) clk=~clk; 
 end 

always@(posedge clk)
 if($time>1000)$stop; 

endmodule 

test_two_2and

这次课，让我学会了
1.如何用VERILOG HDL语言来用and逻辑器件。
2.module的意义。
3.学会定义了时脉的周期。

module top; 


wire A, B, C, T, F;
system_clock #400 clock1(A); 
system_clock #200 clock2(B);
system_clock #100 clock3(C);

and a1(T, A, B);
and a2(F, T, C);

endmodule 

module system_clock(clk); 
parameter PERIOD=100; 
output clk; 
reg clk; 

initial clk=0; 

always 
 begin 
#(PERIOD/2) clk=~clk; 
 end 

always@(posedge clk)
 if($time>1000)$stop; 

endmodule