Verilog结构化设计，模拟出下脚位信号

module top;

wire a,b,c,d;
wire out;

 system_clock #800 clock1(a);
 system_clock #400 clock2(b);
 system_clock #200 clock3(c);
 system_clock #100 clock4(d);

not n0(nota,a);
not n1(notb,b);
not n2(notc,c);
not n3(notd,d);
and a0(f0,nota,notc,d);
and a1(f1,nota,c,notd);
and a2(f2,notb,notc,d);
and a3(f3,notb,c,notd);
or  o0(out,f0,f1,f2,f3);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>2000)$stop;
endmodule

1位Register

因为从低电平开始,所以第一个周期的前半周期的qout是未知的.
module top;
wire data,clock;
reg qout;

system_clock #200 clock1(data);
system_clock #100 clock2(clock);

always@(posedge clock)
begin
   qout=data;
end
endmodule
   
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule

用真值表做出模拟

out=a'b'c+a'cd'+abc'd'+ab'c'd+abcd


module top;

 wire a,b,c,d;
 wire out;

 system_clock #800 clock1(a);
 system_clock #400 clock2(b);
 system_clock #200 clock3(c);
 system_clock #100 clock4(d);

not n0(nota,a);
not n1(notb,b);
not n2(notc,c);
not n3(notd,d);
and a0(f0,nota,notb,c);
and a1(f1,nota,c,notd);
and a2(f2,a,b,notc,notd);
and a3(f3,a,notb,notc,d);
and a4(f4,a,b,c,d);
or  o0(out,f0,f1,f2,f3,f4);



endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>2000)$stop;
endmodule

8位元多工器

SEL=0 选择[7:0]A

SEL=1 选择[7:0]B

module top;

 wire [7:0]a,b;

 wire sel;

 wire [7:0]out;

 system_clock #100 clock1(a[0]); 

 system_clock #100 clock2(a[1]); 

 system_clock #100 clock3(a[2]); 

 system_clock #100 clock4(a[3]); 

 system_clock #100 clock5(a[4]); 

 system_clock #100 clock6(a[5]); 

 system_clock #100 clock7(a[6]);

 system_clock #100 clock8(a[7]);

 system_clock #200 clock9(b[0]); 

 system_clock #200 clock10(b[1]); 

 system_clock #200 clock11(b[2]); 

 system_clock #200 clock12(b[3]); 

 system_clock #200 clock13(b[4]); 

 system_clock #200 clock14(b[5]); 

 system_clock #200 clock15(b[6]);

 system_clock #200 clock16(b[7]);

 system_clock #100 clock17(sel);

 mux8 m8(out,a,b,sel);

endmodule

module mux8(OUT,A,B,SEL);

 output [7:0]OUT;

 input [7:0] A,B;

 input SEL;

mux4 m1(OUT[3:0],A[3:0],B[3:0],SEL);

mux4 m2(OUT[7:4],A[7:4],B[7:4],SEL);

endmodule

module mux4(OUT,A,B,SEL);

 output [3:0]OUT;

 input [3:0] A,B;

 input SEL;

mux2 m1(OUT[1:0],A[1:0],B[1:0],SEL);

mux2 m2(OUT[3:2],A[3:2],B[3:2],SEL);

endmodule

module mux2(OUT,A,B,SEL);

 output [1:0]OUT;

 input [1:0] A,B;

 input SEL;

mux1 m1(OUT[0],A[0],B[0],SEL);

mux1 m2(OUT[1],A[1],B[1],SEL);

endmodule

module mux1(OUT, A, B, SEL);

 output OUT;

 input A,B;

 input SEL;

 not n1(NOT_SEL, SEL);

 and a1 (X, A, NOT_SEL);

 and a2 (Y, SEL, B);

 or  o1 (OUT, X, Y);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk;

initial clk=0;

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end

always@(posedge clk)

 if($time>1000)$stop; 

endmodule

4位元全加器(两个2位元构成)

module top;
  integer ia[3:0],ib[3:0];
  integer icin;
  reg [3:0]a,b;
  reg cin;
  wire cout;
  wire [3:0]sum;

 add_behavioral add4(cout,sum,a,b,cin);

  initial
    begin
      for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)
        begin
          a[0]= ia[0];
          for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+ 1)
            begin
              a[1] = ia[1];
               for (ia[2]=0; ia[2]<=1; ia[2] = ia[2]+ 1)
                begin
                 a[2] = ia[2];
                  for (ia[3]=0; ia[3]<=1; ia[3] = ia[3]+ 1)
                   begin
                     a[3] = ia[3];
                     for (ib[0]=0; ib[0]<=1; ib[0] = ib[0]+1)
                       begin
                         b[0] = ib[0];
                          for (ib[1]=0; ib[1]<=1; ib[1] = ib[1]+ 1)
                           begin
                             b[1] = ib[1];
                             for (ib[2]=0; ib[2]<=1; ib[2] = ib[2]+1)
                               begin
                                 b[2] = ib[2];
                                  for (ib[3]=0; ib[3]<=1; ib[3] = ib[3]+ 1)
                                     begin
                                      b[3] = ib[3];
                                     for (icin=0; icin<=1; icin = icin + 1)
                                        begin
                                      cin = icin;
                 #1 $display("a[0]=%d a[1]=%d a[2]=%d a[3]=%d b[0]=%d b[1]=%d b[2]=%d b[3]=%d sum[0]=%d sum[1]=%d  sum[2]=%d sum[3]=%d cout=%d cin=%d ",a[0],a[1],a[2],a[3],b[0],b[1],b[2],b[3],sum[0],sum[1],sum[2],sum[3],cout,cin);
                      end
                    end
                  end
                end
             end
          end
       end
     end
   end
 end
endmodule

module  add_behavioral(cout,sum,a,b,cin);
 output [3:0]sum;
 output cout;
 input [3:0] a,b;
 input cin;
 wire t;

add2 a1(t,sum[1:0],a[1:0],b[1:0],cin);
add2 a2(cout,sum[3:2],a[3:2],b[3:2],t);

endmodule

module add2(cout,sum,a,b,cin);
 output [1:0]sum;
 output cout;
 input [1:0] a,b;
 input cin;
 wire t;

add1 a1(t,sum[0],a[0],b[0],cin);
add1 a2(cout,sum[1],a[1],b[1],t);

endmodule

module add1(cout,sum,a,b,cin);
 output cout,sum;
 input a,b,cin;
 wire a,b,cin;
 reg cout,sum;

always @(a or b or cin)
 begin
   cout = (cin & (a^b)) | (a&b);
   sum =  (cin ^(a^b));
 end

endmodule

2位全加器

module top;
  integer ia[1:0],ib[1:0];
  integer icin;
  reg [1:0]a,b;
  reg cin;
  wire cout;
  wire [1:0]sum;

 add_behavioral add2(cout,sum,a,b,cin);

  initial
    begin
      for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)
        begin
          a[0]= ia[0];
          for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+ 1)
            begin
              a[1] = ia[1];
               for (ib[0]=0; ib[0]<=1; ib[0] = ib[0]+1)
                 begin
                   b[0] = ib[0];
                    for (ib[1]=0; ib[1]<=1; ib[1] = ib[1]+ 1)
                     begin
                      b[1] = ib[1];
                        for (icin=0; icin<=1; icin = icin + 1)
                       begin
                        cin = icin;
                 #1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d sum[0]=%d sum[1]=%d cout=%d cin=%d ",a[0],a[1],b[0],b[1],sum[0],sum[1],cout,cin);
                      end
                    end
                  end
              end
         end
    end
endmodule

module add_behavioral(cout,sum,a,b,cin);
 output [1:0]sum;
 output cout;
 input [1:0] a,b;
 input cin;
 wire t;

add1 a1(t,sum[0],a[0],b[0],cin);
add1 a2(cout,sum[1],a[1],b[1],t);

endmodule

module add1(cout,sum,a,b,cin);
 output cout,sum;
 input a,b,cin;
 wire a,b,cin;
 reg cout,sum;

always @(a or b or cin)
 begin
   cout = (cin & (a^b)) | (a&b);
   sum =  (cin ^(a^b));
 end

endmodule

1位全加器

1结构模式
module top;
wire A, B, A0 , B0 , C0 , Cin , Sum, Cout;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(Cin);
and a1(A0, A,B);
xor x1(B0, A,B);
and a2(C0, B0,Cin);
or  o1(Cout, A0, C0);
xor x2(Sum, B0 , Cin);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule

2行为模式
module top;
  integer A0,B0,Cin0;
  reg  A,B,Cin;
  wire Cout,Sum;
  mux_behavioral mux1(Cout,Sum,A,B,Cin);
  initial
    begin
      for (A0=0; A0<=1; A0 = A0+1)
        begin
          A = A0;
          for (B0=0; B0<=1; B0 = B0+1)
            begin
              B = B0;
               for (Cin0=0; Cin0<=1; Cin0 = Cin0+1)
                 begin
                   Cin = Cin0;
                 #1 $display("A=%d B=%d Cin=%d ",A,B,Cin,Cout,Sum);
                 end
             end
         end
    end
endmodule
module mux_behavioral(Cout,Sum,A,B,Cin);
 output Cout,Sum;
 input A,B,Cin;
 wire  A,B,Cin;
 reg   Cout,Sum;
always @(A or B or Cin)
 begin
   Cout = (Cin & (A^B)) | (A&B);
   Sum =  (Cin ^(A^B));
 end
endmodule

HIERARCHY 的行为模式2位元多工器

本次学到:矩阵与接线的位元定义[]前后放的不一样

module top;
  integer is;
  integer ia[1:0],ib[1:0];
  reg [1:0]a,b;
  reg s;
  wire [1:0]out;

  mux_behavioral mux2(out,a,b,s);

  initial
    begin
      for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)
        begin
          a[0]= ia[0];
          for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+ 1)
            begin
              a[1] = ia[1];
               for (ib[0]=0; ib[0]<=1; ib[0] = ib[0]+1)
                 begin
                   b[0] = ib[0];
                    for (ib[1]=0; ib[1]<=1; ib[1] = ib[1]+ 1)
                     begin
                      b[1] = ib[1];
                        for (is=0; is<=1; is = is + 1)
                       begin
                        s = is;
                 #1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d s=%d out[0]%d out[1]%d",a[0],a[1],b[0],b[1],s,out[0],out[1]);
                      end
                    end
                  end
              end
         end
    end
endmodule

module mux_behavioral(OUT,A,B,SEL);
 output [1:0]OUT;
 input [1:0] A,B;
 input SEL;

mux1 X1(OUT[0],A[0],B[0],SEL);
mux1 X2(OUT[1],A[1],B[1],SEL);

endmodule

module mux1(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;

 not n1(NOT_SEL, SEL);
 and a1 (X, A, NOT_SEL);
 and a2 (Y, SEL, B);
 or  o1 (OUT, X, Y);

endmodule

行为模式 2位元多工器件

s=1 out0=a0
       out1=a1
s=0 out0=b0
       out1=b1



module top;
  integer ia0,ia1,ib0,ib1,is;
  reg  a0,a1,b0,b1,s;
  wire out1,out2;

  mux_behavioral mux1(out1,out2,a0,a1,b0,b1,s);

  initial
    begin
      for (ia0=0; ia0<=1; ia0 = ia0+1)
        begin
          a0 = ia0;
          for (ia1=0; ia1<=1; ia1 = ia1+ 1)
            begin
              a1 = ia1;
               for (ib0=0; ib0<=1; ib0 = ib0+1)
                 begin
                   b0 = ib0;
                   for (ib1=0; ib1<=1; ib1 = ib1+ 1)
                    begin
                     b1 = ib1;
                      for (is=0; is<=1; is = is + 1)
                       begin
                        s = is;
                 #1 $display("a0=%d a1=%d b0=%d b1=%d s=%d out1=%d out2=%d",a0,a1,b0,b1,s,out1,out2);
                       end
                    end
                  end
              end
         end
   end
endmodule

module mux_behavioral(OUT1,OUT2,A0,A1,B0,B1,SEL);
 output OUT1,OUT2;
 input A0,A1,B0,B1,SEL;
 wire  A0,A1,B0,B1,SEL;
 reg   OUT1,OUT2;

always @(A0 or A1 or B0 or B1 or SEL)
 begin
   OUT1 = (A0 & SEL)|(B0 & ~SEL );
   OUT2 = (A1 & SEL)|(B1 & ~SEL );
 end
endmodule

2位多工器

这次课程，更深刻理解模拟的意义。

器件的延迟效应与周期的设置应该相互匹配，不然会出现很多复杂的不需要的脉冲。

module top;

wire A0, A1, B0, B1, SEL , NOT_SEL , X , Y , Z, W, OUT0, OUT1;

system_clock #1600clock1(A0);
system_clock #800clock2(A1);
system_clock #400clock3(B0);
system_clock #200 clock4(B1);
system_clock #100 clock5(SEL);

not n1(NOT_SEL, SEL);

and a1(X, A0, SEL);
and a2(Y, A1, SEL);
and a3(Z, B0, NOT_SEL);
and a4(W, B1, NOT_SEL);

or o1(OUT0, X , Z);
or o2(OUT1, Y , W);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>2000)$stop;

endmodule


test_four_practice1位多工器

module top;
wire A, B, SEL , NOT_SEL , X , Y , OUT;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(SEL);
not n1(NOT_SEL, SEL);
and a1(X, A, NOT_SEL);
and a2(Y,SEL, B);
or o1(OUT, X , Y);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule

test_three_practice

这是关于二选一选择器的设计的模拟。
本次学习的疑问在于
1.module top与module mux的差别。
2.OUT中瞬间产生的尖刺电压。



module top; 

wire A, B, SEL , NOT_SEL , X , Y , OUT;

system_clock #400 clock1(A); 
system_clock #200 clock2(B);
system_clock #100 clock3(SEL);

not n1(NOT_SEL, SEL);

and a1(X, A, SEL);
and a2(Y, NOT_SEL, B);

or o1(OUT, X , Y);

endmodule 

module system_clock(clk); 
parameter PERIOD=100; 
output clk; 
reg clk; 

initial clk=0; 

always 
 begin 
#(PERIOD/2) clk=~clk; 
 end 

always@(posedge clk)
 if($time>1000)$stop; 

endmodule 

test_two_2and

这次课，让我学会了
1.如何用VERILOG HDL语言来用and逻辑器件。
2.module的意义。
3.学会定义了时脉的周期。

module top; 


wire A, B, C, T, F;
system_clock #400 clock1(A); 
system_clock #200 clock2(B);
system_clock #100 clock3(C);

and a1(T, A, B);
and a2(F, T, C);

endmodule 

module system_clock(clk); 
parameter PERIOD=100; 
output clk; 
reg clk; 

initial clk=0; 

always 
 begin 
#(PERIOD/2) clk=~clk; 
 end 

always@(posedge clk)
 if($time>1000)$stop; 

endmodule 

test_one_and