1位Register

因为从低电平开始,所以第一个周期的前半周期的qout是未知的.
module top;
wire data,clock;
reg qout;

system_clock #200 clock1(data);
system_clock #100 clock2(clock);

always@(posedge clock)
begin
   qout=data;
end
endmodule
   
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule