test_four_practice1位多工器

module top;
wire A, B, SEL , NOT_SEL , X , Y , OUT;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(SEL);
not n1(NOT_SEL, SEL);
and a1(X, A, NOT_SEL);
and a2(Y,SEL, B);
or o1(OUT, X , Y);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule