用真值表做出模拟

out=a'b'c+a'cd'+abc'd'+ab'c'd+abcd


module top;

 wire a,b,c,d;
 wire out;

 system_clock #800 clock1(a);
 system_clock #400 clock2(b);
 system_clock #200 clock3(c);
 system_clock #100 clock4(d);

not n0(nota,a);
not n1(notb,b);
not n2(notc,c);
not n3(notd,d);
and a0(f0,nota,notb,c);
and a1(f1,nota,c,notd);
and a2(f2,a,b,notc,notd);
and a3(f3,a,notb,notc,d);
and a4(f4,a,b,c,d);
or  o0(out,f0,f1,f2,f3,f4);



endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>2000)$stop;
endmodule