1位全加器

1结构模式
module top;
wire A, B, A0 , B0 , C0 , Cin , Sum, Cout;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(Cin);
and a1(A0, A,B);
xor x1(B0, A,B);
and a2(C0, B0,Cin);
or  o1(Cout, A0, C0);
xor x2(Sum, B0 , Cin);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule

2行为模式
module top;
  integer A0,B0,Cin0;
  reg  A,B,Cin;
  wire Cout,Sum;
  mux_behavioral mux1(Cout,Sum,A,B,Cin);
  initial
    begin
      for (A0=0; A0<=1; A0 = A0+1)
        begin
          A = A0;
          for (B0=0; B0<=1; B0 = B0+1)
            begin
              B = B0;
               for (Cin0=0; Cin0<=1; Cin0 = Cin0+1)
                 begin
                   Cin = Cin0;
                 #1 $display("A=%d B=%d Cin=%d ",A,B,Cin,Cout,Sum);
                 end
             end
         end
    end
endmodule
module mux_behavioral(Cout,Sum,A,B,Cin);
 output Cout,Sum;
 input A,B,Cin;
 wire  A,B,Cin;
 reg   Cout,Sum;
always @(A or B or Cin)
 begin
   Cout = (Cin & (A^B)) | (A&B);
   Sum =  (Cin ^(A^B));
 end
endmodule