8位元多工器

SEL=0 选择[7:0]A

SEL=1 选择[7:0]B

module top;

 wire [7:0]a,b;

 wire sel;

 wire [7:0]out;

 system_clock #100 clock1(a[0]); 

 system_clock #100 clock2(a[1]); 

 system_clock #100 clock3(a[2]); 

 system_clock #100 clock4(a[3]); 

 system_clock #100 clock5(a[4]); 

 system_clock #100 clock6(a[5]); 

 system_clock #100 clock7(a[6]);

 system_clock #100 clock8(a[7]);

 system_clock #200 clock9(b[0]); 

 system_clock #200 clock10(b[1]); 

 system_clock #200 clock11(b[2]); 

 system_clock #200 clock12(b[3]); 

 system_clock #200 clock13(b[4]); 

 system_clock #200 clock14(b[5]); 

 system_clock #200 clock15(b[6]);

 system_clock #200 clock16(b[7]);

 system_clock #100 clock17(sel);

 mux8 m8(out,a,b,sel);

endmodule

module mux8(OUT,A,B,SEL);

 output [7:0]OUT;

 input [7:0] A,B;

 input SEL;

mux4 m1(OUT[3:0],A[3:0],B[3:0],SEL);

mux4 m2(OUT[7:4],A[7:4],B[7:4],SEL);

endmodule

module mux4(OUT,A,B,SEL);

 output [3:0]OUT;

 input [3:0] A,B;

 input SEL;

mux2 m1(OUT[1:0],A[1:0],B[1:0],SEL);

mux2 m2(OUT[3:2],A[3:2],B[3:2],SEL);

endmodule

module mux2(OUT,A,B,SEL);

 output [1:0]OUT;

 input [1:0] A,B;

 input SEL;

mux1 m1(OUT[0],A[0],B[0],SEL);

mux1 m2(OUT[1],A[1],B[1],SEL);

endmodule

module mux1(OUT, A, B, SEL);

 output OUT;

 input A,B;

 input SEL;

 not n1(NOT_SEL, SEL);

 and a1 (X, A, NOT_SEL);

 and a2 (Y, SEL, B);

 or  o1 (OUT, X, Y);

endmodule

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk;

initial clk=0;

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end

always@(posedge clk)

 if($time>1000)$stop; 

endmodule